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24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio 19-5332; rev 1; 10/12 ordering information general description the max11200/max11210 are ultra-low-power (< 300fa active current), high-resolution, serial output adcs. these devices provide the highest resolution per unit power in the industry, and are optimized for applications that require very high dynamic range with low power, such as sensors on a 4ma to 20ma industrial control loop. optional input buffers provide isolation of the sig- nal inputs from the switched capacitor sampling network allowing these converters to be used with high-imped- ance sources without compromising available dynamic range or linearity. the devices provide a high-accuracy internal oscillator that requires no external components. when used with the specified data rates, the internal digital filter provides more than 100db rejection of 50hz or 60hz line noise. the devices are configurable using the spi interface and include four gpios that can be used for external mux control. the max11210 includes digital programmable gain of 1, 2, 4, 8, or 16. the max11200/max11210 operate over the -40nc to +85nc temperature range, and are available in a 16-pin qsop package. applications sensor measurement (temperature and pressure) portable instrumentation battery applications weigh scales features s 24.0-bit enob at 5sps 20.9-bit noise-free resolution at 10sps 19-bit noise-free resolution at 120sps s 570nv rms noise at 10sps, q3.6v fs input s 1ppm inl (typ), 10ppm (max) s no missing codes s ultra-low power dissipation operating-mode current drain < 300a (max) sleep-mode current drain < 0.4a s programmable gain (1, 2, 4, 8, or 16) (max11210) s four spi-controlled gpios for external mux control s 2.7v to 3.6v analog supply voltage range s 1.7v to 3.6v digital and i/o supply voltage range s fully differential signal and reference inputs s high-impedance inputs optional input buffers on both signal and reference inputs s programmable internal clock or external clock mode s > 100db (min) 50hz/60hz rejection s spi-, qspi?-, microwire m -compatible serial interface s on-demand offset and gain self-calibration and system calibration s user-programmable offset and gain registers s -40c to +85c operating temperature range s q2kv esd protection s lead(pb)-free and rohs-compliant qsop package +denotes a lead(pb)-free/rohs-compliant package. qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corp. max is a registered trademark of maxim integrated products, inc. selector guide part temp range pin-package max11200eee+ -40c to +85c 16 qsop max11210eee+ -40c to +85c 16 qsop resolution (bits) 4-wire spi, 16-pin qsop, programmable gain 4-wire spi, 16-pin qsop 2-wire serial, 10-pin max ? 24 max11210 max11200 max11201 (with buffers) max11202 (without buffers) 20 max11206 max11207 max11208 18 max11209 max11211 max11212 16 max11213 max11203 max11205 max11200/max11210 evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. any pin to gnd .................................................... -0.3v to +3.9v avdd to gnd ....................................................... -0.3v to +3.9v dvdd to gnd ...................................................... -0.3v to +3.9v analog inputs (ainp, ainn, refp, refn) to gnd ............................................. -0.3v to (v avdd + 0.3v) digital inputs and digital outputs to gnd ............................................. -0.3v to (v dvdd + 0.3v) esd hb (avdd, ainp, ainn, refp, refn, dvdd, clk, cs, sclk, din, rdy/dout, gnd, gpio_) ........... q2kv (note 1) continuous power dissipation (t a = +70nc) 16-pin qsop (derate 8.3mw/nc above +70nc) .......... 667mw operating temperature range .......................... -40nc to +85nc junction temperature ..................................................... +150nc storage temperature range ............................ -55nc to +150nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc electrical characteristics (v avdd = +3.6v, v dvdd = +1.7v, v refp - v refn = v avdd ; internal clock, single-cycle mode (scycle = 1), t a = t min to t max , unless otherwise noted. typical values are at t a = +25nc under normal conditions, unless otherwise noted.) absolute maximum ratings note 1: human body model to specification mil-std-883 method 3015.7. parameter symbol conditions min typ max units static performance noise-free resolution (notes 2, 3) nfr 120sps 19 bits 10sps 20.9 noise (notes 2, 3) v n 120sps 2.1 fv rms 10sps 0.57 integral nonlinearity inl at 10sps (note 4) -10 +10 ppmfsr zero error after self and system calibration, v refp - v refn = 2.5v -10 +10 ppmfsr zero drift 50 nv/nc full-scale error after self and system calibration, v refp - v refn = 2.5v (note 5) -20 +20 ppmfsr full-scale error drift 0.05 ppmfsr/ nc power-supply rejection avdd dc rejection 70 80 db dvdd dc rejection 90 100 analog inputs/reference inputs common-mode rejection cmr dc rejection 90 123 db 50hz/60hz rejection at 120sps 90 50hz/60hz rejection at 1sps to 15sps 144 normal-mode 50hz rejection nmr 50 linef = 1, for 1sps to 15sps (notes 6, 7) 100 144 db normal-mode 60hz rejection nmr 60 linef = 0, for 1sps to 15sps (notes 6, 7) 100 144 db common-mode voltage range ain buffers disabled v gnd v avdd v maxim integrated max11200/max11210
3 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio electrical characteristics (continued) (v avdd = +3.6v, v dvdd = +1.7v, v refp - v refn = v avdd ; internal clock, single-cycle mode (scycle = 1), t a = t min to t max , unless otherwise noted. typical values are at t a = +25nc under normal conditions, unless otherwise noted.) parameter symbol conditions min typ max units absolute input voltage low input voltage buffers disabled v gnd - 30mv v buffers enabled v gnd + 100mv high input voltage buffers disabled v avdd + 30mv buffers enabled v avdd - 100mv dc input leakage sleep mode q1 fa ain dynamic input current buffer disabled q1.4 fa/v buffer enabled q20 na ref dynamic input current buffer disabled q2.1 fa/v buffer enabled q30 na ain input capacitance buffer disabled 5 pf ref input capacitance buffer disabled 7.5 pf ain voltage range unipolar 0 v ref v bipolar -v ref +v ref input sampling rate f s linef = 0 246 khz linef = 1 204.8 ref voltage range buffers disabled 0 v avdd v buffers enabled 0.1 v avdd - 0.1 ref sampling rate linef = 0 246 khz linef = 1 204.8 logic inputs (sclk, clk, din, gpio1Cgpio4) input current input leakage current q1 fa input low voltage v il 0.3 x v dvdd v input high voltage v ih 0.7 x v dvdd v input hysteresis v hys 200 mv external clock 60hz line frequency 2.4576 mhz 55hz line frequency 2.25275 50hz line frequency 2.048 logic outputs (rdy/dout, gpio1Cgpio4) output low level v ol i ol = 1ma; also tested for v dvdd = 3.6v 0.4 v output high level v oh i oh = 1ma; also tested for v dvdd = 3.6v 0.9 x v dvdd v leakage current high-impedance state q500 na output capacitance high-impedance state 9 pf maxim integrated max11200/max11210
4 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio electrical characteristics (continued) (v avdd = +3.6v, v dvdd = +1.7v, v refp - v refn = v avdd ; internal clock, single-cycle mode (scycle = 1), t a = t min to t max , unless otherwise noted. typical values are at t a = +25nc under normal conditions, unless otherwise noted.) note 2: these specifications are not fully tested and are guaranteed by design and/or characterization. note 3: v ainp = v ainn . note 4: ppmfsr is parts per million of full scale. note 5: positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges. note 6: for data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps. note 7: normal-mode rejection of power line frequencies of 60hz/50hz apply only for single-cycle data rates at 15sps/10sps and lower or continuous data rate of 60sps/50sps. parameter symbol conditions min typ max units power requirements analog supply v avdd 2.7 3.6 v digital supply v dvdd 1.7 3.6 v total operating current avdd + dvdd buffers disabled 235 300 fa buffers enabled 255 avdd sleep current 0.15 2 fa avdd operating current buffers disabled 185 235 fa buffers enabled 205 dvdd sleep current 0.25 2 fa dvdd operating current 50 65 fa spi timing characteristics sclk frequency f sclk 5 mhz sclk clock period t cp 200 ns sclk pulse-width high t ch 80 ns sclk pulse-width low t cl 60% duty cycle at 5mhz 80 ns cs low to 1st sclk rise setup t css0 40 ns cs high to 17th sclk setup t css1 40 ns cs high after 16th sclk falling edge hold t csh1 3 ns cs pulse-width high t csw 40 ns din to sclk setup t ds 40 ns din hold after sclk t dh 0 ns rdy/dout transition valid after sclk fall t dot output transition time, data changes on falling edge of sclk 40 ns rdy/dout remains valid after sclk fall t doh output hold time allows for negative edge data read 3 ns rdy/dout valid before sclk rise t dol t dol = t cl - t dot 40 ns cs rise to rdy/dout disable t dod c load = 20pf 25 ns cs fall to rdy/dout valid t doe default value of rdy is 1 for minimum specification; maximum specification for valid 0 on rdy/dout 0 40 ns data fetch t df maximum time after rdy asserts to read data register; t cnv is the time for one conversion 0 t cnv - 60 x t cp maxim integrated max11200/max11210
5 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio typical operating characteristics (v avdd = +3.6v, v dvdd = +1.8v, v refp - v refn = 2.5v; internal clock; t a = t min to t max , unless otherwise noted. typical values are at t a = +25nc.) digital sleep current vs. dvdd voltage max11200/10 toc09 dvdd voltage (v) current (a) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 1.9 0.5 1.0 1.5 2.0 2.5 3.0 0 1.7 t a = +85c t a = +25c t a = -45c digital active current vs. dvdd voltage max11200/10 toc08 dvdd voltage (v) current (a) 3.4 3.2 2.8 3.0 2.0 2.2 2.4 2.6 1.8 50 60 70 80 90 100 110 120 130 40 1.6 3.6 t a = -45c, +25c, +85c linef = 0 linef = 1 t a = +85c t a = -45c sleep current vs. temperature max11200/10 toc07 temperature (c) current (a) 75 55 35 15 -5 -25 0.2 0.4 0.6 0.8 1.0 0 -45 95 total dvdd avdd active supply current vs. temperature (linef = 1) max11200/10 toc06 temperature (c) current (a) 75 55 35 15 -5 -25 50 100 150 200 250 300 0 -45 95 v dvdd = 1.8v v avdd = 3.0v total active supply current vs. temperature (linef = 0) max11200/10 toc05 temperature (c) current (a) 75 55 35 15 -5 -25 50 100 150 200 250 300 0 -45 95 v dvdd = 1.8v v avdd = 3.0v total analog sleep current vs. avdd voltage max11200/10 toc04 avdd voltage (v) current (a) 3.4 3.5 3.3 3.2 3.1 3.0 2.9 2.8 0.2 0.4 0.6 0.8 1.0 0 2.7 3.6 t a = -45c, +25c, +85c t a = +85c t a = -45c analog active current vs. avdd voltage (signal and reference buffers enabled) max11200/10 toc03 avdd voltage (v) current (a) 3.45 3.30 3.15 3.00 2.85 180 200 220 240 260 280 160 2.70 3.60 t a = +85c t a = +25c t a = -45c analog active current vs. avdd voltage (signal or reference buffers enabled) max11200/10 toc02 avdd voltage (v) current (a) 3.45 3.30 3.15 3.00 2.85 140 160 180 200 220 240 260 120 2.70 3.60 signal buffer s t a = +85c t a = +25c t a = -45c analog active current vs. avdd voltage (no buffers enabled) max11200/10 toc01 avdd voltage (v) current (a) 3.45 3.30 3.15 3.00 2.85 140 160 180 200 220 240 260 120 2.70 3.60 linef = 0, linef = 1 linef = 1 t a = +85c t a = +25c t a = -45c maxim integrated max11200/max11210
6 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio typical operating characteristics (continued) (v avdd = +3.6v, v dvdd = +1.8v, v refp - v refn = 2.5v; internal clock; t a = t min to t max , unless otherwise noted. typical values are at t a = +25nc.) cmrr vs. frequency max11200/10 toc18 frequency (hz) cmrr (db) 10,000 1000 100 10 -120 -100 -80 -60 -40 -20 0 -140 1 100,000 10sps 120sps psrr vs. frequency (data rate 10sps) max11200/10 toc17 frequency (hz) psrr (db) 10,000 1000 100 10 -120 -100 -80 -60 -40 -20 0 -140 1 100,000 dvdd avdd psrr vs. frequency (data rate 120sps) max11200/10 toc16 frequency (hz) psrr (db) 10,000 1000 100 10 -120 -100 -80 -60 -40 -20 0 -140 1 100,000 dvdd avdd tue vs. input voltage max11200/10 toc15 input voltage (v) inl (ppmfsr) 2.0 1.5 0.5 1.0 -1.5 -1.0 -0.5 0 -2.0 -8 -6 -4 -2 0 2 4 6 8 10 -10 -2.5 2.5 t a = +85c t a = -45c t a = +25c vin(cm) = 1.8v integral nonlinearity vs. input voltage max11200/10 toc14 input voltage (v) inl (ppmfsr) 2.0 1.5 0.5 1.0 -1.5 -1.0 -0.5 0 -2.0 -8 -6 -4 -2 0 2 4 6 8 10 -10 -2.5 2.5 t a = +85c t a = -45c t a = +25c vin(cm) = 1.8v long-term adc readings max11200/10 toc13 time (minutes) adc reading (v) 2.5 2.0 1.5 1.0 0.5 -4 -3 -2 -1 0 1 2 3 4 5 -5 0 3.0 shorted inputs rms noise = 570nv t a = +25c noise vs. input voltage max11200/10 toc12 input voltage (v) noise (v rms ) 2.0 1.5 0.5 1.0 -1.5 -1.0 -0.5 0 -2.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -2.5 2.5 internal oscillator frequency vs. avdd voltage max11200/10 toc11 avdd voltage (v) frequency (mhz) 3.45 3.15 3.30 3.00 2.85 1.7 1.6 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 1.5 2.70 3.60 linef = 1 linef = 0 internal oscillator frequency vs. temperature max11200/10 toc10 temperature (c) frequency (mhz) 75 55 15 35 -5 -25 1.7 1.6 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 1.5 -45 95 v avdd = 3.0v linef = 1 linef = 0 maxim integrated max11200/max11210
7 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio functional diagram timing clock generator digital logic and serial- interface controller digital filter (sinc 4 ) programmable gain* (1?16) 3rd-order delta-sigma modulator sclk din clk gpio cs rdy/dout gpio1 gpio2 gpio3 gpio4 avdd refp refn *programmable gain only available on the max11210. ainp ainn dvdd gnd max11200 max11210 maxim integrated max11200/max11210
8 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio pin description pin configuration pin name function 1 gpio1 general-purpose i/o 1. register controllable using spi. 2 gpio2 general-purpose i/o 2. register controllable using spi. 3 gpio3 general-purpose i/o 3. register controllable using spi. 4 gnd ground. ground reference for analog and digital circuitry. 5 refp differential reference positive input. refp must be more positive than refn. connect refp to a voltage between avdd and gnd. 6 refn differential reference negative input. refn must be more negative than refp. connect refn to a voltage between avdd and gnd. 7 ainn negative fully differential analog input 8 ainp positive fully differential analog input 9 avdd analog supply voltage. connect a supply voltage between +2.7v and +3.6v with respect to gnd. 10 dvdd digital supply voltage. connect a digital supply voltage between +1.7v and +3.6v with respect to gnd. 11 cs active-low, chip-select logic input 12 din serial-data input. data present at din is shifted to the devices internal registers at the rising edge of the serial clock at sclk, when the device is accessed for an internal register write or for a command operation. 13 rdy/dout data ready output/serial-data output. this output serves a dual function. in addition to the serial-data output function, the rdy/dout also indicates that the data is ready when the rdy is logic-low. rdy/ dout changes on the falling edge of sclk. 14 sclk serial-clock input. apply an external serial clock to sclk. 15 clk external clock signal input. when external clock mode is selected (extclk = 1), provide a 2.4576mhz or 2.048mhz clock signal at clk. other frequencies can be used, but the data rate and digital filter notch frequencies scale accordingly. 16 gpio4 general-purpose i/o 4. register controllable using spi. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 gpio1 gpio4 clk sclk rdy/dout din cs dvdd avdd top view qsop gpio2 gpio3 refn gnd refp ainn ainp + max11200 max11210 maxim integrated max11200/max11210
9 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio detailed description the max11200/max11210 are ultra-low-power (< 300fa active), high-resolution, low-speed, serial-output adcs. these adcs provide the highest resolution per unit power in the industry, and are optimized for applications that require very high dynamic range with low power such as sensors on a 4ma to 20ma industrial control loop. optional input buffers provide isolation of the signal inputs from the switched capacitor sampling network, allowing the devices to be used with very high imped- ance sources without compromising available dynamic range. the devices provide a high-accuracy internal oscillator, which requires no external components. when used with the specified data rates, the internal digital fil- ter provides more than 144db rejection of 50hz or 60hz line noise. the devices are highly configurable using the spi interface and include four gpios for external mux control. analog inputs the devices accept two analog inputs (ainp, ainn) in buffered or unbuffered mode. the input buffer isolates the inputs from the capacitive load presented by the modulator, allowing for high source-impedance analog transducers. the value of the sigbuf bit in the ctrl1 register determines whether the input buffer is enabled or disabled. see table 12. input voltage range the modulator input range is programmable for bipolar (-v ref to +v ref ) or unipolar (0 to v ref ) ranges. the u/b bit in the ctrl1 register configures the devices for uni- polar or bipolar transfer functions. see table 12. system clock the devices incorporate a highly stable internal oscillator that provides the system clock. the system clock runs the internal state machine and is trimmed to 2.4576mhz or 2.048mhz. the internal oscillator clock is divided down to run the digital and analog timing. the linef bit in the ctrl1 register determines the internal oscillator frequency. see tables 10 and 12. set linef = 0 to select the 2.4576mhz oscillator and linef = 1 to select the 2.048mhz oscillator. the 2.4576mhz oscillator provides maximum 60hz rejection, and the 2.048mhz oscillator table 1. continuous conversion with scycle bit = 0 table 2. single-cycle conversion with scycle bit = 1 *linef bit = 0 sets the clock frequency to 2.4576mhz and the input sampling frequency to 245.76khz. linef bit = 1 sets the clock frequency to 2.048mhz and the input sampling frequency to 204.8khz. *linef bit = 0 sets the clock frequency to 2.4576mhz and the input sampling frequency to 245.76khz. linef bit = 1 sets the clock frequency to 2.048mhz and the input sampling frequency to 204.8khz. rate[2:0] data rate* (sps) bipolar nfr (bits) bipolar enob (bits) unipolar nfr (bits) unipolar enob (bits) output noise (v rms ) linef = 0 linef = 1 100 60 50 20.5 23.2 19.5 22.2 0.74 101 120 100 20.0 22.7 19.0 21.7 1.03 110 240 200 19.5 22.2 18.5 21.2 1.45 111 480 400 19.0 21.7 18.0 20.7 2.21 rate[2:0] single-cycle data rate* (sps) bipolar nfr (bits) bipolar enob (bits) unipolar nfr (bits) unipolar enob (bits) output noise (v rms ) linef = 0 linef = 1 000 1 0.833 22.3 24.0 21.3 24.0 0.21 001 2.5 2.08 22 24.0 21.0 23.7 0.27 010 5 4.17 21.4 24.0 20.4 23.1 0.39 011 10 8.33 20.9 23.6 19.9 22.6 0.57 100 15 12.5 20.5 23.2 19.5 22.2 0.74 101 30 25 20.0 22.7 19.0 21.7 1.03 110 60 50 19.5 22.2 18.5 21.2 1.45 111 120 100 19.0 21.7 18.0 20.7 2.21 maxim integrated max11200/max11210
10 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio provides maximum 50hz rejection. see figures 1 and 2. for optimal simultaneous 50hz and 60hz rejection, apply a 2.25275mhz external clock at clk. reference the devices provide differential inputs refp and refn for an external reference voltage. connect the external reference directly across the refp and refn to obtain the differential reference voltage. the common-mode voltage range for v refp and v refn is between 0 and v avdd . the devices accept reference inputs in buffered or unbuffered mode. the value of the refbuf bit in the ctrl1 register determines whether the reference buffer is enabled or disabled. see table 12. buffers the devices include reference and signal input buffers capable of reducing the average input current from 2.1fa/v on the reference inputs and from 1.4fa/v on the analog inputs to a constant 30na current on the reference inputs and 20na current on the analog inputs. the reference and signal input buffers can be selected individually by programming the ctrl1 register bits refbuf and sigbuf. when enabled, the reference and input signal buffers require an additional 20fa from the avdd supply pin. power-on reset (por) the devices utilize power-on reset (por) supply monitor- ing circuitry on both the digital supply (dvdd) and the analog supply (avdd). the por circuitry ensures proper device default conditions after either a digital or analog power-sequencing event. the digital por trigger threshold is approximately 1.2v and has 100mv of hysteresis. the analog por trigger threshold is approximately 1.25v and has 100mv of hysteresis. both por circuits have lowpass filters that prevent high-frequency supply glitches from triggering the por. calibration the devices provide two sets of calibration registers which offer the user several options for calibrating the system. the calibration register value defaults are all zero, which require a user to either perform a calibration or pro- gram the register through the spi interface to use them. the on-chip calibration registers are enabled or disabled by programming the nosysg, nosyso, noscg, and nosco bits in the ctrl3 register. the default values for these calibration control bits are 1, which disables the use of the internal calibration registers. the devices power up with the internal calibration regis- ters disabled, and therefore a full-scale input produces a result of 60% of the full-scale digital range. to use the full-scale digital range, a calibration must be performed. the first level of calibration is the self-calibration where the part performs the required connections to zero and full scale internally. this level of calibration is typically sufficient for 1 f v of offset accuracy and 2ppm of full- scale accuracy. the self-calibration routine does not include the source resistance effects from the signal source driving the input pins, which can change the off - set and gain of the system. a second level of calibration is available where the user can calibrate a system zero scale and system full scale by presenting a zero-scale signal or a full-scale signal to the input pins and initiating a system zero scale or system gain calibration command. a third level of calibration allows for the user to write to the internal calibration registers through the spi interface to achieve any digital offset or scaling the user requires with the following restrictions. the range of digital offset correction is qv ref /4. the range of digital gain correc- tion is from 0.5 to 1.5. the resolution of offset correction is 0.5 lsb. the calibration operations are controlled with the cal1 and cal0 bits in the command byte. the user requests a self-calibration by setting the cal1 bit to 0 and cal0 bit to 1. a self-calibration requires 200ms to complete, and both the scoc and scgc registers contain the values that correct the chip output for zero scale and full scale. the user requests a system zero-scale calibration by setting the cal1 bit to 1 and the cal0 bit to 0 and presents a system zero-level signal to the input pins. the system zero calibration requires 100ms to complete, and the soc register contains values that correct the chip zero scale. the user requests a system full-scale calibra- tion by setting the cal1 bit to 1 and the cal0 bit to 1 and presents a system full-scale signal level to the input pins. the system full-scale calibration requires 100ms to complete, and the sgc register contains values that correct for the chip full-scale value. see tables 3a and 3b for an example of a self-calibration sequence and a system-calibration sequence. maxim integrated max11200/max11210
11 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio noise vs. data rate the devices offer software-selectable internal oscillator frequencies as well as software-selectable output data rates. the linef bit in the ctrl1 register (table 12) determines the internal oscillator frequency. the rate bits in the command byte (table 8) determine the adcs output data rate. the devices also offer the option of running in zero latency single-cycle conversion mode (table 2) or continuous conversion mode (table 1). set scycle = 0 in the ctrl1 register (table 12) to run in continuous conversion mode and scycle = 1 for single- cycle conversion mode. single-cycle conversion mode gives an output result with no data latency. the devices output data up to 100sps (2.048mhz internal oscillator) or 120sps (2.4576mhz internal oscillator) with no data latency. in continuous conversion mode, the output data rate is four times the single-cycle conversion mode, for sample rates up to 400sps or 480sps. in continuous conversion mode, the output data requires three additional 24-bit cycles to settle from an input step. digital filter the devices include a sinc 4 digital filter that produces spectral nulls at the multiples of the data rate. for all data rates less than 30sps, a spectral null occurs at the line frequency of 60hz and is guaranteed to attenuate 60hz normal-mode components by more than 100db. simultaneous 50hz and 60hz attenuation can be accom- plished by using an external clock with a frequency of 2.25275mhz. this guarantees a minimum of 80db rejection at 50hz and 85db rejection at 60hz. the sinc 4 filter has a -3db frequency equal to 24% of the data rate. see figures 1 and 2. gpios the devices provide four gpio ports. when set as out- puts, these digital i/os can be used to drive the digital inputs to a multiplexer or multichannel switch. figure 3 details an example where four single-ended signals are multiplexed in a break-before-make switching sequence, using the max313, a quad spst analog switch. the devices gpio ports are configurable through the ctrl2 register. see table 13. to select ain1, write the command to ctrl2 according to table 4a. table 3a. example of self-calibration table 3b. example of system calibration step description register bit scoc scgc soc sgc nosysg nosyso noscg nosco 1 initial power-up 0x000000 0x000000 0x000000 0x000000 1 1 1 1 2 enable self-calibration registers 0x000000 0x000000 0x000000 0x000000 1 1 0 0 3 self-calibration, din = 10010000 0x00007e 0xbfd345 0x000000 0x000000 1 1 0 0 step description register bit scoc scgc soc sgc nosysg nosyso noscg nosco 1 initial power-up 0x000000 0x000000 0x000000 0x000000 1 1 1 1 2 enable self-calibration registers 0x000000 0x000000 0x000000 0x000000 1 1 0 0 3 self-calibration, din = 10010000 0x00007e 0xbfd345 0x000000 0x000000 1 1 0 0 4 enable system offset register 0x00007e 0xbfd345 0x000000 0x000000 1 0 0 0 5 system-calibration offset, din = 1010000 0x00007e 0xbfd345 0xffee1d 0x000000 1 0 0 0 6 enable system gain register 0x00007e 0xbfd345 0xffee1d 0x000000 0 0 0 0 7 system-calibration gain, din = 1011000 0x00007e 0xbfd345 0xffee1d 0x81cb5b 0 0 0 0 maxim integrated max11200/max11210
12 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio figure 1. normal-mode frequency response (2.4576mhz oscillator, linef = 0) figure 2. normal-mode frequency response (2.048mhz oscillator, linef = 1) table 4a. data command to select channel ain1 in figure 3 table 4b. data command to set all channels high impedance in figure 3 normal mode rejection data rate 10.0sps frequency (hz) gain (db) 90 80 60 40 70 30 50 20 10 -130 -140 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -150 0 100 normal mode rejection data rate 120.0sps frequency (hz) gain (db) 1800 1600 1200 800 1400 600 1000 400 200 -130 -140 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -150 0 2000 normal mode rejection data rate 8.333sps frequency (hz) gain (db) 90 80 60 40 70 30 50 20 10 -130 -140 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -150 0 100 normal mode rejection data rate 100.000sps frequency (hz) gain (db) 1800 1600 1200 800 1400 600 1000 400 200 -130 -140 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -150 0 2000 bit b7 b6 b5 b4 b3 b2 b1 b0 bit name dir4 dir3 dir2 dir1 dio4 dio3 dio2 dio1 value 1 1 1 1 0 0 0 1 bit b7 b6 b5 b4 b3 b2 b1 b0 bit name dir4 dir3 dir2 dir1 dio4 dio3 dio2 dio1 value 1 1 1 1 0 0 0 0 maxim integrated max11200/max11210
13 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio this selects all gpio as outputs, as well as setting all logic signals to 0 except the selected channel ain1. to select channel ain3 next, it is best to set all switches to a high-impedance state first (see table 4b). then select channel ain3 by driving in3 high (see table 4c). it is not always necessary to transition to a high-imped- ance state between channel selections, but depends on the source analog signals as well as the control structure of the multiplexed switches. digital programmable gain (max11210) the max11210 offers programmable gain settings that can be digitally set to 1, 2, 4, 8, or 16. the dgain_ bits in the ctrl3 register (table 14) configure the digital gain setting and control the input referred gain. see figure 4. the max11210s input range is 0v to v ref /gain (unipo- lar) or v ref /gain (bipolar). the max11210 modulator produces 32 bits of data, but only 24 bits of data are used. for any given data rate, the noise floor remains constant, independent of the digital gain setting. the max11210 digital gain is beneficial for systems that can afford averaging multiple readings for higher resolution. table 4c. data command to select channel ain3 in figure 3 figure 4. max11210 digital programmable gain example (1sps output rate) figure 3. max11200 gpios drive an external 4-channel switch (max313) bit b7 b6 b5 b4 b3 b2 b1 b0 bit name dir4 dir3 dir2 dir1 dio4 dio3 dio2 dio1 value 1 1 1 1 0 1 0 0 msb lsb noise floor remains constant at 0.21v rms bits used for gain = 16 bits used for gain = 2 bits used for gain = 1 sub-lsbs 24-bit output data cycle v ref = 3.6v, v lsb = 429nv, bipolar range ain1 ain2 ain3 ain4 in1 in2 in3 in4 com1 com2 com3 com4 gpio1 gpio2 gpio3 gpio4 ainp ainn max313 logic switch 0 off 1o n max11200 max313 maxim integrated max11200/max11210
14 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio figure 5. spi command byte figure 6. spi register access write figure 7. spi register access read serial-digital interface the max11200/max11210 interface is fully compatible with spi-, qspi-, and microwire-standard serial inter - faces. the spi interface provides access to nine on-chip registers that are 8 or 24 bits wide. drive cs low to transfer data in and out of the devices. clock in data at din on the rising edge of sclk. the rdy/dout output serves two functions: conversion sta- tus and data read. to find the conversion status, assert cs low and read the rdy/dout output; the conversion is in progress if the rdy /dout output reads logic-high and the conversion is complete if the rdy/dout output reads logic-low. data at rdy/dout changes on the falling edge of sclk and is valid on the rising edge of sclk. din and dout are transferred msb first. drive cs high to force dout high impedance and cause the devices to ignore any signals on sclk and din. figures 5, 6, and 7 show the spi timing diagrams. t csh0 t doe high-z t dod high-z t css0 sclk 0 x 1 10 cal1 cal0 impd rate2 rate1 rate0 8 din t dh t cp t csh1 t css1 t csw t cl t ch t ds cs rdy/dout t csh0 t doe high-z t dod high-z t css0 sclk 0 x 1 11 x rs3 rs2 rs1 rs0 w/r d7 d6 d5 d4 d3 d2 d1 d0 16 89 din t dh t cp t csh1 t css1 t csw t cl t ch t ds cs rdy/dout t doe high-z high-z sclk x 1 11 x rs3 rs2 rs1 rs0 w/r xx x xxx xx d6 d7 d5 d4 d3 d2 d1 d0 16 89 din t cp t dod t dot t do1 t doh cs rdy/dout t css0 t ds t css1 t cl t ch t dh maxim integrated max11200/max11210
15 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio command byte communication between the user and the device is con- ducted through spi using a command byte. the com- mand byte consists of two modes differentiated as com- mand modes and data modes. command modes and data modes are further differentiated by decoding the remaining bits in the command byte. the mode selected is determined by the mode bit. if the mode bit is 0, then the user is requesting either a conversion, calibration, or power-down; see table 5. if the mode bit is 1, then the user is selecting a data command and can either read from or write to a register; see table 6. the status register (stat1) is a read-only register and provides general chip operational status to the user. if the user attempts to calibrate the system and overranges the internal signal scaling, then a gain overrange condi- tion is flagged with the sysor bit. the last data rate programmed for the adc is available in the rate bits. if the input signal has exceeded positive or negative full scale, this condition is flagged with the or and ur bits. if the modulator is busy converting, then the mstat bit is set. if a conversion result is ready for read-out, the rdy bit is set; see table 11. the control 1 register (ctrl1) is a read/write register, and the bits determine the internal oscillator frequency, unipolar or bipolar input range, selection of an internal or external clock, enabling or disabling the reference and input signal buffers, the output data format (offset binary or twos complement), and single-cycle or continuous conversion mode. see table 12. the control 2 register (ctrl2) is a read/write register, and the bits configure the gpios as inputs or outputs and their values. see table 13. the control 3 register (ctrl3) is a read/write register, and the bits determine the max11210 programmable gain setting and the calibration register settings for both the max11200 and max11210. see table 14. the data register (data) is a read-only register. data is output from rdy/dout on the next 24 sclk cycles once cs is forced low. the data bits transition on the falling edge of sclk. data is output msb first, and is offset binary or twos complement, depending on the setting of the format bit in the ctrl1 register. see table 15. the system offset calibration register (soc) is a read/ write register, and the bits contain the digital value that corrects the data for system zero scale. see table 17. the system gain calibration register (sgc) is a read/ write register, and the bits contain the digital value that corrects the data for system full scale. see table 18. the self-calibration offset register (scoc) is a read/ write register, and the bits contain the value that corrects the data for chip zero scale. see table 19. the self-calibration gain register (scgc) is a read/write register, and the bits contain the value that corrects the data for chip full scale. see table 20. table 5. command byte (mode = 0) table 6. command byte (mode = 1) note: the start bit is used to synchronize the data from the host device. the start bit is always 1. bit b7 b6 b5 b4 b3 b2 b1 b0 bit name start = 1 mode = 1 0 rs3 rs2 rs1 rs0 w/r bit b7 b6 b5 b4 b3 b2 b1 b0 bit name start = 1 mode = 0 cal1 cal0 impd rate2 rate1 rate0 maxim integrated max11200/max11210
16 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio table 7. operating mode (mode bit) table 8. command byte (mode = 0, linef = 0) table 9. register selection (mode = 1) mode bit setting operating mode 0 the command byte initiates a conversion or an immediate power-down. see tables 5 and 8. 1 the device interprets the command byte as a register access byte, which is decoded as per tables 6 and 9. command start mode cal1 cal0 impd rate2 rate1 rate0 self-calibration cycle 1 0 0 1 0 0 0 0 system offset calibration cycle 1 0 1 0 0 0 0 0 system gain calibration 1 0 1 1 0 0 0 0 immediate power-down 1 0 0 0 1 0 0 0 convert 1sps 1 0 0 0 0 0 0 0 convert 2.5sps 1 0 0 0 0 0 0 1 convert 5sps 1 0 0 0 0 0 1 0 convert 10sps 1 0 0 0 0 0 1 1 convert 15sps 1 0 0 0 0 1 0 0 convert 30sps 1 0 0 0 0 1 0 1 convert 60sps 1 0 0 0 0 1 1 0 convert 120sps 1 0 0 0 0 1 1 1 rs3 rs2 rs1 rs0 register access power-on reset status register size (bits) 0 0 0 0 stat1 0x00 8 0 0 0 1 ctrl1 0x02 8 0 0 1 0 ctrl2 0x0f 8 0 0 1 1 ctrl3 0x1e 8 0 1 0 0 data 0x000000 24 0 1 0 1 soc 0x000000 24 0 1 1 0 sgc 0x000000 24 0 1 1 1 scoc 0x000000 24 1 0 0 0 scgc 0x000000 24 maxim integrated max11200/max11210
17 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio table 10. register address map *these dgain_ bits set the digital gain for the max11210. these bits are dont-care bits for the max11200. register name r/w address select (rs[3:0]) b7 b6 b5 b4 b3 b2 b1 b0 stat1 r 0x0 sysor rate2 rate1 rate0 or ur mstat rdy ctrl1 r/w 0x1 linef u/b extclk refbuf sigbuf format scycle reserved ctrl2 r/w 0x2 dir4 dir3 dir2 dir1 dio4 dio3 dio2 dio1 ctrl3 r/w 0x3 dgain2* dgain1* dgain0* nosysg nosyso noscg nosco reserved data r 0x4 d[23:16] d[15:8] d[7:0] soc r/w 0x5 b[23:16] b[15:8] b[7:0] sgc r/w 0x6 b[23:16] b[15:8] b[7:0] scoc r/w 0x7 b[23:16] b[15:8] b[7:0] scgc r/w 0x8 b[23:16] b[15:8] b[7:0] maxim integrated max11200/max11210
18 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio stat1: status register sysor: the system gain overrange bit when set to 1 indicates that a system gain calibration was over range. the scgc calibration coefficient is maximum value of 1.9999999. this bit, when set to 1, indicates that the full-scale value out of the converter is likely not available. rate[2:0]: the data rate bits indicate the conversion rate that corresponds to the result in the data register or the rate that was used for calibration coefficient calculation. if the previous conversions were done at a different rate, the rate[2:0] bits indicate a rate different than the rate of the conversion in progress. or: the overrange bit, or, is set to 1 to indicate the conversion result has exceeded the maximum value of the converter and that the result has been clipped or limited to the maximum value. the or bit is set to 0 to indicate the conversion result is within the full-scale range of the device. ur: the underrange bit, ur, is set to 1 to indicate the conversion result has exceeded the minimum value of the converter and that the result has been clipped or limited to the minimum value. the ur bit is set to 0 to indicate the conversion result is within the full-scale range of the device. mstat: the measurement status bit, mstat is set to 1 when a signal measurement is in progress. when mstat = 1, a conversion, self-calibration, or system calibration is in progress and indicates that the modulator is busy. when the modulator is not converting, the mstat bit is set to 0. rdy: the rdy ready bit is set to 1 to indicate that a conversion result is available. reading the data register resets the rdy bit to 0 only after another conversion has been initiated. if the data has not been read before another conversion is initiated, the rdy bit remains 1; if the data is read before another conversion is initiated, the rdy bit resets to 0. if the data for the previous conversion is read during a following conversion, the rdy bit is reset immediately after the data read operation has completed. table 11. stat1 register (read only) bit b7 b6 b5 b4 b3 b2 b1 b0 bit name sysor rate2 rate1 rate0 or ur mstat rdy default 0 0 0 0 0 0 0 0 maxim integrated max11200/max11210
19 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio ctrl1: control 1 register the byte-wide ctrl1 register is a bidirectional read/write register. the byte written to the ctrl1 register indicates if the part converts continuously or single cycle, if an external or internal clock is used, if the reference and signal buffers are activated, the format of the data when in bipolar mode, and if the analog signal input range is unipolar or bipolar. linef: use the line frequency bit, linef, to select if the data rate is centered for 50hz power mains or 60hz power mains. to select data rates for 50hz power mains, write 1 to linef and to select data rates for 60hz power mains, write 0 to linef. u/b: the unipolar/bipolar bit, u/b, selects if the input range is unipolar or bipolar. a 1 in this bit location selects a uni- polar input range and a 0 selects a bipolar input range. extclk: the external clock bit, extclk, controls the selection of the system clock. a 1 enables an external clock as system clock, whereas as a 0 enables the internal clock. refbuf: the reference buffer bit, refbuf, enables/disables the reference buffers. a 1 enables the reference buffers. a 0 powers down the reference buffers and the reference inputs bypass the reference buffers when driving the adc. sigbuf: the signal buffer, sigbuf, enables/disables the signal buffers. a 1 enables the signal buffer. a 0 powers down the signal buffers and the analog signal inputs bypass the signal buffers when driving the adc. format: the format bit, format, controls the digital format of the data. unipolar data is always in offset binary for- mat. the bipolar format is twos complement if the format bit is set to 0 or offset binary if the format bit is set to 1. scycle: the single-cycle bit, scycle, determines if the device runs in no-latency single-conversion mode (scycle = 1) or if the device runs in latent continuous-conversion mode (scycle = 0). when in single-cycle conver - sion mode, the device completes one no-latency conversion and then powers down into a leakage-only state. when in continuous-conversion mode, the part is continuously converting and the first three data from the part are incorrect due to the sinc 4 filter latency. important note: when operating in continuous-conversion mode (scycle = 0), it is recommended to keep cs low to properly detect the end of conversion. the end of conversion is signaled by rdy/dout changing from 0 to 1. the tran- sition of rdy /dout from 0 to 1 must be used to synchronize the data register read back. if the rdy /dout output is not used to synchronize the data read back, a timing hazard exists where the data register is updated internally after a conversion has completed simultaneously with the data register being read out, causing an incorrect read of data. table 12. ctrl1 register (read/write) bit b7 b6 b5 b4 b3 b2 b1 b0 bit name linef u/b extclk refbuf sigbuf format scycle unused default 0 0 0 0 0 0 1 0 maxim integrated max11200/max11210
20 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio ctrl2: control 2 register the byte-wide ctrl2 register is a bidirectional read/write register. the byte written to the ctrl2 register controls the direction and values of the digital i/o ports. dir[4:1]: the direction bits configure the direction of the dio bit. when a dir bit is set to 0, the associated dio bit is configured as an input and the value returned by a read of the dio bit is the value being driven on the associated gpio. when a dir bit is set to 1, the associated dio bit is configured as an output and the gpio port is driven to a logic value of the associated dio bit. dio[4:1]: the data input/output bits are bits associated with the gpio ports. when a dio is configured as an input, the value read from the dio bit is the logic value being driven at the gpio port. when the direction is configured as an output, the gpio port is driven to a logic value associated with the dio bit. ctrl3: control 3 register the byte-wide ctrl3 register is a bidirectional read/write register. the ctrl3 register controls the operation and calibration of the device. dgain[2:0] (max11210 only): the digital gain bits control the input referred gain. with a gain of 1, the input range is 0 to v ref (unipolar) or v ref (bipolar). as the gain in increased by 2x, the input range is reduced to 0 to v ref /gain or v ref /gain. digital gain is applied to the final offset and gain-calibrated digital data. the dgain[2:0] bits decode to digital gains as follows: 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 nosysg: the no-system gain bit, nosysg, controls the system gain calibration coefficient. a 1 in this bit location disables the use of the system gain value when computing the final offset and gain corrected data value. a 0 in this location enables the use of the system gain value when computing the final offset and gain corrected data value. nosyso: the no system offset bit, nosyso, controls the system offset calibration coefficient. a 1 in this location disables the use of the system offset value when computing the final offset and gain corrected data value. a 0 in this location enables the use of the system offset value when computing the final offset and gain corrected data value. noscg: the no self-calibration gain bit, noscg, controls the self-calibration gain coefficient. a 1 in this location disables the use of the self-calibration gain value when computing the final offset and gain corrected data value. a 0 in this location enables the use of the self-calibration gain value when computing the final offset and gain corrected data value. nosco: the no self-calibration offset bit, nosco, controls the use of the self-calibration offset coefficient. a 1 in this location disables the use of the self-calibration offset value when computing the final offset and gain corrected data value. a 0 in this location enables the use of the self-calibration offset value when computing the final offset and gain corrected data value. table 13. ctrl2 register (read/write) table 14. ctrl3 register (read/write) *these dgain_ bits are dont-care bits for the max11200. bit b7 b6 b5 b4 b3 b2 b1 b0 bit name dir4 dir3 dir2 dir1 dio4 dio3 dio2 dio1 default 0 0 0 0 1 1 1 1 bit b7 b6 b5 b4 b3 b2 b1 b0 bit name dgain2* dgain1* dgain0* nosysg nosyso noscg nosco reserved default 0 0 0 1 1 1 1 0 maxim integrated max11200/max11210
21 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio data: data register the data register is a 24-bit read-only register. any attempt to write data to the data register has no effect. the data read from this register is clocked out msb first. the data register holds the conversion result. d23 is the msb, and d0 is the lsb. the result is stored in a format according to the format bit in ctrl1 register. the data format while in unipolar mode is always straight binary. in straight binary format, the most negative value is 0x000000 (v ainp - v ainn = 0v), the midscale value is 0x800000 (v ainp - v ainn = v ref /2), and the most positive value is 0xffffff (v ainp - v ainn = v ref ). in bipolar mode, if the format bit = 1, then the data format is offset binary. if the format bit = 0, then the data for- mat is twos complement. in twos complement, the negative full-scale value is 0x800000 (v ainp - v ainn = -v ref ), the midscale is 0x000000 (v ainp - v ainn = 0v), and the positive full scale is 0x7fffff (v ainp - v ainn = v ref ). any input exceeding the available input range is limited to the minimum or maximum data value. table 15. data register (read only) table 16a. output data format for the unipolar input range bit d23 d22 d21 d20 d19 d18 d17 d16 default 0 0 0 0 0 0 0 0 bit d15 d14 d13 d12 d11 d10 d9 d8 default 0 0 0 0 0 0 0 0 bit d7 d6 d5 d4 d3 d2 d1 d0 default 0 0 0 0 0 0 0 0 input voltage v ainp - v ainn digital output code for unipolar range straight binary format v ref 0xffffff ref 24 1 v1 21 ?? ? ?? ? ?? 0xfffffe ref 24 v 21 ? 0x000001 0 0x000000 maxim integrated max11200/max11210
22 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio table 16b. output data formats for the bipolar input range table 17. soc register (read/write) soc: system offset calibration register the system offset calibration register is a 24-bit read/write register. the data written/read to/from this register is clocked in/out msb (most significant bit) first. this register holds the system offset calibration value. the format is always in twos complement binary format. a write to the system-calibration register is allowed. the value written remains valid until it is either rewritten or until an on-demand system-calibration operation is performed, which overwrites the user- supplied value. the system offset calibration value is subtracted from each conversion result provided the nosyso bit in the ctrl3 register is set to 0. the system offset calibration value is subtracted from the conversion result after self-calibration but before system gain correction. the system offset calibration value is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes. bit b23 b22 b21 b20 b19 b18 b17 b16 default 0 0 0 0 0 0 0 0 bit b15 b14 b13 b12 b11 b10 b9 b8 default 0 0 0 0 0 0 0 0 bit b7 b6 b5 b4 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 input voltage v ainp - v ainn digital output code for bipolar ranges offset binary format twos complement format v ref 0xffffff 0x7fffff ref 23 1 v1 21 ?? ? ?? ? ?? 0xfffffe 0x7ffffe ref 23 v 21 ? 0x800001 0x000001 0 0x800000 0x000000 ref 23 v 21 ? ? 0x7fffff 0xffffff ref 23 1 v1 21 ?? ? ? ?? ? ?? 0x000001 0x800001 -v ref 0x000000 0x800000 maxim integrated max11200/max11210
23 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio scoc: self-calibration offset register the self-calibration offset register is a 24-bit read/write register. the data written/read to/from this register is clocked in/out msb first. this register holds the self-calibration offset value. the format is always in twos complement binary format. a write to the self-calibration offset register is allowed. the written value remains valid until it is either rewritten or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value. the self-calibration offset value is subtracted from each conversion result provided the nosco bit in the ctrl3 reg- ister is set to 0. the self-calibration offset value is subtracted from the conversion result before the self-calibration gain correction and before the system offset and gain correction. the self-calibration offset value is also applied prior to the 2x scale factor associated with unipolar mode. table 18. sgc register (read/write) table 19. scoc register (read/write) sgc: system gain calibration register the system gain calibration register is a 24-bit read/write register. the data written/read to/from this register is clocked in/out msb first. this register holds the system gain calibration value. the format is always in twos complement binary format. a write to the system-calibration register is allowed. the written value remains valid until it is either rewritten or until an on-demand system-calibration operation is performed, which overwrites the user-supplied value. the system gain calibration value is used to scale the offset corrected conversion result, provided the nosysg bit in the ctrl3 register is set to 0. the system gain calibration value scales the offset-corrected result by up to 2x or corrects a gain error of approximately -50%. the amount of positive gain error that can be corrected is determined by modulator overload characteristics, which can be as much as +25%. the gain is corrected to within 2 lsb. bit b23 b22 b21 b20 b19 b18 b17 b16 default 0 0 0 0 0 0 0 0 bit b15 b14 b13 b12 b11 b10 b9 b8 default 0 0 0 0 0 0 0 0 bit b7 b6 b5 b4 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 bit b23 b22 b21 b20 b19 b18 b17 b16 default 0 0 0 0 0 0 0 0 bit b15 b14 b13 b12 b11 b10 b9 b8 default 0 0 0 0 0 0 0 0 bit b7 b6 b5 b4 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 maxim integrated max11200/max11210
24 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio table 20. scgc register (read/write) scgc: self-calibration gain register the self-calibration gain register is a 24-bit read/write register. the data written/read to/from this register is clocked in/ out msb first. this register holds the self-calibration gain value. the format is always in twos complement binary format. a write to the self-calibration gain register is allowed. the written value remains valid until it is either rewritten or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value. any attempt to write to this register during an active calibration operation is ignored. the self-calibration gain value is used to scale the self-calibration offset corrected conversion result before the system offset and gain calibration values have been applied, provided the noscg bit in the ctrl3 register is set to 0. the self-calibration gain value scales the self-calibration offset corrected conversion result by up to 2x or can correct a gain error of approximately -50%. the gain is corrected to within 2 lsb. table 21. data rates for all combinations of rate[2:0] (linef = 0) table 22. data rates for all combinations of rate[2:0] (linef = 1) bit b23 b22 b21 b20 b19 b18 b17 b16 default 0 0 0 0 0 0 0 0 bit b15 b14 b13 b12 b11 b10 b9 b8 default 0 0 0 0 0 0 0 0 bit b7 b6 b5 b4 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 rate[2:0] single-cycle data rate (sps) continuous data rate (sps) 000 1 001 2.5 010 5 011 10 100 15 60 101 30 120 110 60 240 111 120 480 rate[2:0] single-cycle data rate (sps) continuous data rate (sps) 000 0.833 001 2.08 010 4.17 011 8.33 100 12.5 50 101 25 100 110 50 200 111 100 400 maxim integrated max11200/max11210
25 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio figure 8. rtd temperature measurement circuit applications information see figure 8 for the rtd temperature measurement circuit and figure 9 for a resistive bridge measurement circuit. magnetic force restoration (mfr) force-measuring (typi- cally weight) systems are a good design example requir- ing an adc that has exceptional dynamic range and lin - earity. mfr devices use a lever and fulcrum to balance an unknown weight (the object to be measured) with an electromagnetic force coil. the current necessary to keep the balance in equilibrium is equal to the force of gravity exerted to the object to be weighed. these currents can be as large as several hundred amperes, or as small as several microamperes, all in the same system. often, it is necessary to maintain the given accuracy across the entire scale. this application requires a quantizing device with enough resolution and dynamic range to match the sen- sor system. in the past, this was done using an audio adc and dac under the control of a microprocessor to build a discrete delta-modulator-style a/d. this was very expensive, and could decrease the mean time between failure (mtbf) for measurement devices requiring high reliability. the max11200/max11210 adcs offer a much simpler solution with excellent resolution and dynamic range. see figure 10. chip information process: bicmos figure 9. resistive bridge measurement circuit i ref2 i ref1 i ref1 = k x i ref2 refp refn r ref ainp ainn gnd r rtd max11200 max11210 refp avdd refn ainp ainn max11200 max11210 maxim integrated max11200/max11210
26 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio figure 10. typical magnetic force restoration scale package information for the latest package outline information and land patterns, go to www.maximintegrated.com/packages. note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 qsop e16+4 21-0055 90-0167 gate array cpu e 2 prom keyboard display p/d part magnet load force coi l tension flexure fulcrum flexures rs-232c temperature adc temperature sensor weighing pan roberval beam photodiode output resistance weight adc current drive part maxim integrated max11200/max11210
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 27 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. 24-bit, single-channel, ultra-low-power, delta-sigma adcs with gpio revision history revision number revision date description pages changed 0 6/10 initial release 1 10/12 updated the serial-digital interface section 14 max11200/max11210

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